Computer Architecture, Microprocessors & MicrocontrollersComputer Architecture, Microprocessors & Microcontrollers

How a CPU is built inside, how it runs instructions fast, and how tiny chips control machines.CPU ভেতরে কীভাবে তৈরি, কীভাবে instruction দ্রুত চালায়, আর ছোট chip কীভাবে machine control করে।

In this chapterএই chapter-এ যা আছে

CPU OrganizationCPU Organization
Instruction Sets & Addressing ModesInstruction Sets & Addressing Modes
PipeliningPipelining
Cache & Memory HierarchyCache & Memory Hierarchy
I/O OrganizationI/O Organization
Microprocessors & MicrocontrollersMicroprocessors & Microcontrollers
Practice QuestionsPractice Questions

1. CPU Organization1. CPU Organization

The CPU (Central Processing Unit) is the brain of the computer. It reads instructions from memory and runs them one by one. To understand a computer, first understand how the CPU and memory are connected.

Von Neumann vs Harvard architecture

There are two classic ways to connect CPU and memory:

Von Neumann architecture: Program (instructions) and data live in the same memory. One bus carries both. This is the "stored program" idea. Most PCs follow this style.
Harvard architecture: Instructions and data live in separate memories, with separate buses. The CPU can fetch an instruction and read data at the same time. Many microcontrollers (like AVR) use this.

CPU (Central Processing Unit) হলো computer-এর brain। এটা memory থেকে instruction পড়ে আর এক এক করে চালায়। Computer বুঝতে হলে আগে বুঝতে হবে CPU আর memory কীভাবে connect করা।

Von Neumann vs Harvard architecture

CPU আর memory connect করার দুইটা classic উপায় আছে:

Von Neumann architecture: Program (instruction) আর data একই memory-তে থাকে। একটা bus দুটোই বহন করে। এটাই "stored program" idea। বেশিরভাগ PC এই style follow করে।
Harvard architecture: Instruction আর data আলাদা memory-তে থাকে, bus-ও আলাদা। CPU একসাথে instruction fetch আর data read করতে পারে। অনেক microcontroller (যেমন AVR) এটা use করে।

Von Neumann architecture block diagram: CPU with control unit and ALU, memory, input and output — Von Neumann architecture: one memory holds both program and data.Von Neumann architecture: একটা memory-তেই program আর data দুটোই থাকে।

Harvard architecture: two separate memories, two separate buses.Harvard architecture: দুইটা আলাদা memory, দুইটা আলাদা bus।

PointPoint	Von Neumann	Harvard
MemoryMemory	One memory for program + dataProgram + data এক memory-তে	Separate program and data memoryProgram আর data memory আলাদা
BusesBus	One shared busএকটা shared bus	Separate busesআলাদা bus
Fetch data + instruction together?Data + instruction একসাথে fetch?	No (bottleneck)না (bottleneck হয়)	Yes (faster)হ্যাঁ (দ্রুত)
Cost / designCost / design	Simple, cheapSimple, সস্তা	More hardware, costlierHardware বেশি, দাম বেশি
Used inকোথায় use হয়	General PCs, laptopsসাধারণ PC, laptop	Microcontrollers, DSP chipsMicrocontroller, DSP chip

Note: The shared bus of Von Neumann creates the famous "Von Neumann bottleneck" — CPU must wait because instruction fetch and data access share one path. Exams love this term. Von Neumann-এর shared bus তৈরি করে বিখ্যাত "Von Neumann bottleneck" — instruction fetch আর data access এক path share করে বলে CPU-কে wait করতে হয়। Exam-এ এই term খুব আসে।

Main parts of the CPU

ALU (Arithmetic Logic Unit): does the math (add, subtract) and logic (AND, OR, compare).
CU (Control Unit): the manager. It decodes instructions and sends control signals telling every part what to do and when.
Registers: very small, very fast storage inside the CPU. They hold the data the CPU is using right now.

Common registers

CPU-এর প্রধান অংশ

ALU (Arithmetic Logic Unit): math (add, subtract) আর logic (AND, OR, compare) করে।
CU (Control Unit): manager। Instruction decode করে আর control signal পাঠিয়ে বলে দেয় কোন অংশ কখন কী করবে।
Register: CPU-এর ভেতরের খুব ছোট, খুব fast storage। CPU এখন যে data নিয়ে কাজ করছে সেটা এখানে থাকে।

Common register

Register	Full nameFull name	What it holdsকী রাখে
PC	Program Counter	Address of the next instruction to fetchপরের যে instruction fetch হবে তার address
IR	Instruction Register	The instruction currently being executedএখন যে instruction execute হচ্ছে সেটা
MAR	Memory Address Register	The memory address CPU wants to read/writeCPU যে memory address read/write করতে চায়
MDR / MBR	Memory Data (Buffer) Register	The data going to or coming from memoryMemory-তে যাওয়া বা memory থেকে আসা data
ACC	Accumulator	Result of ALU operationsALU operation-এর result
SP	Stack Pointer	Address of the top of the stackStack-এর top-এর address

Instruction cycle: fetch → decode → execute

The CPU repeats one simple loop forever:

Fetch: bring the next instruction from memory into IR.
Decode: CU figures out what the instruction means.
Execute: do the actual work (ALU operation, memory read/write, or jump).

Instruction cycle: fetch → decode → execute

CPU একটা simple loop বারবার repeat করে:

Fetch: পরের instruction-টা memory থেকে IR-এ আনে।
Decode: CU বুঝে নেয় instruction-টার মানে কী।
Execute: আসল কাজটা করে (ALU operation, memory read/write, বা jump)।

Example:

Step-by-step register transfer for the instruction LOAD 500 (copy the value at memory address 500 into ACC). Suppose PC = 100.

Fetch:

MAR ← PC (MAR = 100)
MDR ← M[MAR] (read instruction from address 100)
IR ← MDR (instruction now in IR)
PC ← PC + 1 (PC = 101, ready for next instruction)

Decode: CU sees opcode = LOAD, operand address = 500.

Execute:

MAR ← 500
MDR ← M[500] (read the data)
ACC ← MDR (data is now in ACC)

LOAD 500 instruction-এর (memory address 500-এর value ACC-তে copy করা) step-by-step register transfer। ধরি PC = 100।

Fetch:

MAR ← PC (MAR = 100)
MDR ← M[MAR] (address 100 থেকে instruction read)
IR ← MDR (instruction এখন IR-এ)
PC ← PC + 1 (PC = 101, পরের instruction-এর জন্য ready)

Decode: CU দেখে opcode = LOAD, operand address = 500।

Execute:

MAR ← 500
MDR ← M[500] (data read করা)
ACC ← MDR (data এখন ACC-তে)

Buses

A bus is a group of wires shared by CPU, memory, and I/O. There are three:

Data bus: carries the actual data. Bidirectional (both ways).
Address bus: carries the memory address the CPU wants. Unidirectional (CPU → memory only).
Control bus: carries control signals like Read, Write, Interrupt, Clock.

What bus width means

Bus width = number of wires = number of bits carried at once.

An n-bit address bus can point to $2^n$ different memory locations.
A wider data bus moves more bits per transfer, so it is faster.

Bus

Bus হলো একগুচ্ছ wire, যেটা CPU, memory আর I/O share করে। তিন ধরনের bus আছে:

Data bus: আসল data বহন করে। Bidirectional (দুই দিকেই যায়)।
Address bus: CPU যে memory address চায় সেটা বহন করে। Unidirectional (শুধু CPU → memory)।
Control bus: Read, Write, Interrupt, Clock-এর মতো control signal বহন করে।

Bus width মানে কী

Bus width = wire-এর সংখ্যা = একসাথে কত bit যায়।

n-bit address bus মোট $2^n$ টা আলাদা memory location point করতে পারে।
Data bus যত wide, এক transfer-এ তত বেশি bit যায়, তাই তত fast।

\[ \text{Addressable locations} = 2^{\text{address bus width}} \]

Example:

The Intel 8086 has a 20-bit address bus. So it can address $2^{20} = 1{,}048{,}576$ locations = 1 MB of memory. A modern 32-bit address bus gives $2^{32}$ = 4 GB. A 16-bit address bus gives $2^{16} = 65{,}536$ = 64 KB.

Intel 8086-এর 20-bit address bus আছে। তাই এটা $2^{20} = 1{,}048{,}576$ টা location address করতে পারে = 1 MB memory। আধুনিক 32-bit address bus দেয় $2^{32}$ = 4 GB। 16-bit address bus দেয় $2^{16} = 65{,}536$ = 64 KB।

Note: Exam trick: "address bus width" controls how much memory you can reach ($2^n$); "data bus width" controls how fast you move it. Do not mix them up. Exam trick: "address bus width" ঠিক করে কতটুকু memory reach করা যায় ($2^n$); "data bus width" ঠিক করে কত দ্রুত data যায়। দুটো গুলিয়ে ফেলবেন না।

2. Instruction Sets & Addressing Modes2. Instruction Sets & Addressing Modes

Machine language vs assembly language

Machine language: pure binary (0s and 1s). This is the only language the CPU understands directly. Example: 10110000 00000101.
Assembly language: the same instructions but written with short readable names (mnemonics) like MOV, ADD, JMP. A program called an assembler converts assembly into machine code. One assembly line = one machine instruction.

Instruction format

Every instruction has two parts:

Opcode: says what to do (ADD, LOAD, JUMP...).
Operand(s): says on what — a register, a memory address, or a constant.

Machine language vs assembly language

Machine language: খাঁটি binary (0 আর 1)। CPU সরাসরি শুধু এটাই বোঝে। Example: 10110000 00000101।
Assembly language: একই instruction, কিন্তু ছোট readable নাম (mnemonic) দিয়ে লেখা — যেমন MOV, ADD, JMP। Assembler নামের program assembly-কে machine code-এ convert করে। এক assembly line = এক machine instruction।

Instruction format

প্রতিটা instruction-এর দুইটা অংশ:

Opcode: বলে কী করতে হবে (ADD, LOAD, JUMP...)।
Operand: বলে কীসের উপর — কোনো register, memory address, বা constant।

Example:

A 16-bit instruction with a 4-bit opcode and a 12-bit address field:

| opcode (4 bits) | address (12 bits) |

4-bit opcode → $2^4 = 16$ possible instructions. 12-bit address → $2^{12} = 4096$ memory words can be addressed.

16-bit instruction, যেখানে 4-bit opcode আর 12-bit address field:

| opcode (4 bits) | address (12 bits) |

4-bit opcode → $2^4 = 16$ টা সম্ভব instruction। 12-bit address → $2^{12} = 4096$ টা memory word address করা যায়।

Addressing modes

An addressing mode is the rule for finding the operand. Same opcode, different ways to say "where the data is". These come in exams again and again.

Addressing mode

Addressing mode হলো operand খুঁজে পাওয়ার নিয়ম। Opcode একই, কিন্তু "data কোথায়" বলার উপায় আলাদা। Exam-এ এগুলো বারবার আসে।

Mode	Where is the operand?Operand কোথায়?	ExampleExample
Immediate	Inside the instruction itself (a constant)Instruction-এর ভেতরেই (একটা constant)	`MOV A, #5` (A = 5)(A = 5)
Direct	Instruction gives the memory addressInstruction-এ memory address দেওয়া থাকে	`LOAD 500` (ACC = M[500])(ACC = M[500])
Indirect	Instruction gives an address that holds the address of the dataInstruction-এ এমন address থাকে যেখানে data-র address রাখা	`LOAD (500)` (ACC = M[M[500]])(ACC = M[M[500]])
Register	In a CPU registerCPU register-এ	`ADD R1, R2`
Register indirect	A register holds the memory addressRegister-এ memory address রাখা থাকে	`LOAD (R1)` (ACC = M[R1])(ACC = M[R1])
Indexed	Address = base in instruction + index registerAddress = instruction-এর base + index register	`LOAD 100(X)` (ACC = M[100 + X])(ACC = M[100 + X])
Relative	Address = PC + offset in instructionAddress = PC + instruction-এর offset	`JMP +8` (go to PC + 8)(PC + 8-এ যাও)

Example:

Suppose memory holds: M[500] = 600, M[600] = 900, and register R1 = 500. What does ACC get for the operand "500" in each mode?

Immediate (LOAD #500): ACC = 500 (the number itself).
Direct (LOAD 500): ACC = M[500] = 600.
Indirect (LOAD (500)): ACC = M[M[500]] = M[600] = 900.
Register indirect (LOAD (R1)): ACC = M[R1] = M[500] = 600.

This exact style of question appears in admission tests: same number, four different answers.

ধরি memory-তে আছে: M[500] = 600, M[600] = 900, আর register R1 = 500। প্রতিটা mode-এ operand "500"-এর জন্য ACC কী পাবে?

Immediate (LOAD #500): ACC = 500 (সংখ্যাটাই)।
Direct (LOAD 500): ACC = M[500] = 600।
Indirect (LOAD (500)): ACC = M[M[500]] = M[600] = 900।
Register indirect (LOAD (R1)): ACC = M[R1] = M[500] = 600।

Admission test-এ ঠিক এই style-এর প্রশ্ন আসে: একই সংখ্যা, চারটা আলাদা answer।

RISC vs CISC

Two big design philosophies for instruction sets:

RISC vs CISC

Instruction set design-এর দুইটা বড় philosophy:

PointPoint	RISC (Reduced Instruction Set Computer)	CISC (Complex Instruction Set Computer)
InstructionsInstruction	Few, simpleঅল্প, simple	Many, complexঅনেক, complex
Instruction sizeInstruction size	Fixed lengthFixed length	Variable lengthVariable length
Execution timeExecution time	Mostly 1 clock cycle per instructionবেশিরভাগ instruction 1 clock cycle-এ	Multiple cycles per instructionএক instruction-এ একাধিক cycle
Memory accessMemory access	Only LOAD/STORE touch memoryশুধু LOAD/STORE memory touch করে	Many instructions can touch memoryঅনেক instruction-ই memory touch করতে পারে
RegistersRegister	Many registersঅনেক register	Fewer registersকম register
Addressing modesAddressing mode	Fewকম	Manyঅনেক
PipeliningPipelining	Easy (fixed-size instructions)সহজ (fixed-size instruction)	Harderকঠিন
Control unitControl unit	HardwiredHardwired	MicroprogrammedMicroprogrammed
Program sizeProgram size	Longer programs (more instructions)Program বড় হয় (instruction বেশি লাগে)	Shorter programsProgram ছোট হয়
ExamplesExample	ARM, MIPS, RISC-V	Intel x86 (8086, Pentium)

Note: Asked October 2018 (flow diagram form): the exam asked to compare CISC and RISC as a flow diagram. Easy trick: draw two vertical flows. CISC: complex instruction → microprogrammed control unit breaks it into many micro-steps → multiple cycles → result. RISC: simple fixed-size instruction → hardwired control decodes in one step → 1 cycle in the pipeline → result. Label each arrow with the matching row from this table. October 2018-এ এসেছে (flow diagram আকারে): exam-এ CISC আর RISC-কে flow diagram আকারে compare করতে বলেছিল। সহজ trick: দুইটা উল্লম্ব flow আঁকুন। CISC: complex instruction → microprogrammed control unit অনেক micro-step-এ ভাঙে → একাধিক cycle → result। RISC: simple fixed-size instruction → hardwired control এক step-এ decode করে → pipeline-এ 1 cycle → result। প্রতিটা arrow-তে এই table-এর matching row-টা লিখে দিন।

0, 1, 2, 3-address instructions

Machines differ in how many operand addresses one instruction can name. Classic exam task: write the same expression in all four styles. Let us compute:

0, 1, 2, 3-address instruction

এক instruction-এ কয়টা operand address লেখা যায়, machine ভেদে সেটা আলাদা। Classic exam task: একই expression চার style-এ লেখা। আমরা compute করব:

\[ X = (A + B) \times (C - D) \]

3-address (result and two sources all named):

3-address (result আর দুই source সবই লেখা থাকে):

ADD R1, A, B      ; R1 = A + B
SUB R2, C, D      ; R2 = C - D
MUL X,  R1, R2    ; X = R1 * R2

2-address (first operand is also the destination):

2-address (প্রথম operand-টাই destination):

MOV R1, A         ; R1 = A
ADD R1, B         ; R1 = R1 + B
MOV R2, C         ; R2 = C
SUB R2, D         ; R2 = R2 - D
MUL R1, R2        ; R1 = R1 * R2
MOV X,  R1        ; X = R1

1-address (everything goes through ACC; T is a temporary memory cell):

1-address (সব কিছু ACC দিয়ে হয়; T একটা temporary memory cell):

LOAD  A           ; ACC = A
ADD   B           ; ACC = ACC + B
STORE T           ; T = ACC        (A+B saved)
LOAD  C           ; ACC = C
SUB   D           ; ACC = ACC - D
MUL   T           ; ACC = ACC * T
STORE X           ; X = ACC

0-address (stack machine; operations use the top two stack items):

0-address (stack machine; operation stack-এর top দুইটা item use করে):

PUSH A
PUSH B
ADD               ; stack top = A + B
PUSH C
PUSH D
SUB               ; stack top = C - D
MUL               ; stack top = (A+B)*(C-D)
POP  X            ; X = result

Note: BUET-style exams often say: "Write a program to evaluate X = ... using a 0-address / 1-address machine." Practice converting the expression to postfix first for the 0-address (stack) case — the PUSH/operation order follows the postfix form exactly. For $(A+B)\times(C-D)$, postfix is A B + C D - *. BUET-style exam-এ প্রায়ই বলে: "0-address / 1-address machine দিয়ে X = ... evaluate করার program লেখো।" 0-address (stack) case-এর জন্য আগে expression-টা postfix-এ convert করার practice করুন — PUSH/operation-এর order ঠিক postfix form-টাই follow করে। $(A+B)\times(C-D)$-এর postfix হলো A B + C D - *।

A Tiny Bit of Assembly (Real Exam Questions!)

PUSH and POP under the hood. PUSH and POP look special, but they are really just a mov plus an add/subtract on the stack pointer (SP). The stack grows downward — toward smaller addresses — and SP points to the item on top. So:

PUSH X = first make room (move SP down by 1), then store X there.
POP X = first copy the top item into X, then free the slot (move SP up by 1).

A Tiny Bit of Assembly (Real Exam Questions!)

PUSH আর POP-এর ভেতরের কাহিনী। PUSH আর POP দেখতে special, কিন্তু আসলে এরা শুধু একটা mov আর stack pointer (SP)-এর উপর একটা add/subtract। Stack নিচের দিকে বাড়ে — ছোট address-এর দিকে — আর SP সবসময় top-এর item-টা point করে। তাহলে:

PUSH X = আগে জায়গা বানাও (SP-কে 1 নামাও), তারপর সেখানে X store করো।
POP X = আগে top-এর item X-এ copy করো, তারপর slot-টা ছেড়ে দাও (SP-কে 1 ওঠাও)।

; PUSH X  (using only mov and add/sub)
sub sp, sp, #1        ; same as: add sp, sp, -1   → SP moves DOWN
mov [sp], X           ; store X at the new top

; POP X
mov X, [sp]           ; copy the top item into X
add sp, sp, #1        ; SP moves UP → old top is now free

Address       before        after PUSH 7        (stack grows down ↓)
  103       |  ...   |      |  ...   |
  102       |   5    | ←SP  |   5    |
  101       |  free  |      |   7    | ←SP
  100       |  free  |      |  free  |

Note: Asked April 2019. SP moves opposite to intuition: PUSH makes SP smaller, POP makes it bigger, because the stack grows toward lower addresses. Also watch the order: PUSH moves SP first, then writes; POP reads first, then moves SP. Swapping the order corrupts the stack. April 2019-এ এসেছে। SP intuition-এর উল্টা চলে: PUSH করলে SP ছোট হয়, POP করলে বড়, কারণ stack ছোট address-এর দিকে বাড়ে। Order-টাও খেয়াল করুন: PUSH আগে SP সরায়, তারপর লেখে; POP আগে পড়ে, তারপর SP সরায়। Order উল্টালে stack নষ্ট হয়ে যাবে।

Why conditional branches can only jump a short distance

A conditional branch (like BEQ label) uses PC-relative addressing: the instruction stores a small signed offset, and target = PC + offset. That offset must fit inside the fixed instruction format — and after the opcode, condition, and register bits are placed, only a few bits are left for it.

Example: with a 16-bit offset field, the reachable range is only $-2^{15}$ to $+2^{15}-1$ → about ±32K from the current PC. An unconditional jump instruction has almost the whole instruction free for the address, so it can reach much farther.

How to branch far anyway: flip the condition and hop over an unconditional jump (a "trampoline"):

Conditional branch কেন শুধু কাছেই jump করতে পারে

Conditional branch (যেমন BEQ label) use করে PC-relative addressing: instruction-এ একটা ছোট signed offset থাকে, আর target = PC + offset। Offset-টাকে fixed instruction format-এর ভেতরে আঁটতে হয় — আর opcode, condition, register bit বসানোর পরে এর জন্য মাত্র কয়েকটা bit-ই বাকি থাকে।

Example: offset field 16-bit হলে reach করা যায় শুধু $-2^{15}$ থেকে $+2^{15}-1$ → বর্তমান PC থেকে প্রায় ±32K। Unconditional jump instruction-এ address-এর জন্য প্রায় পুরো instruction-টাই free, তাই সেটা অনেক দূরে যেতে পারে।

তাহলে দূরে branch করব কীভাবে: condition উল্টে দিয়ে একটা unconditional jump-এর উপর দিয়ে লাফ দিন (একটা "trampoline"):

; Want: BEQ far_label    (but far_label is out of range)
    BNE skip          ; opposite condition, tiny jump (in range)
    JMP far_label     ; unconditional jump — long range
skip:
    ...

Note: Asked April 2019: "Why do conditional branch instructions have a limited addressing range?" One-line answer: because they keep the target as a small PC-relative offset inside a fixed-size instruction, and the offset field has only a few bits. April 2019-এ এসেছে: "Conditional branch instruction-এর addressing range limited কেন?" One-line answer: কারণ এরা target-কে রাখে fixed-size instruction-এর ভেতরে একটা ছোট PC-relative offset হিসেবে, আর সেই offset field-এ মাত্র কয়েকটা bit থাকে।

How Hardware Divides — Shift and Subtract (Restoring Division)

A CPU has no magic "divide" circuit. It divides the same way you do long division on paper: shift, compare, subtract. This is called restoring division. Setup: put the dividend in register Q, the divisor in register M, and clear a remainder register A to 0. Then repeat, once per bit of the dividend:

Shift left the pair (A, Q) by one bit — the top bit of Q slides into A. This "brings down" the next dividend bit, just like paper long division.
Subtract: try A = A − M.
Check the borrow: if the result is not negative (no borrow), the divisor "fits" — set the new quotient bit Q₀ = 1. If the result is negative (borrow happened), the divisor did not fit — restore A by adding M back, and set Q₀ = 0.

After n steps (n = number of bits), Q holds the quotient and A holds the remainder. So division is really just repeated shift-and-subtract — hardware only needs a shifter, a subtractor (adder), and a control loop.

Hardware কীভাবে ভাগ করে — Shift and Subtract (Restoring Division)

CPU-তে কোনো magic "divide" circuit নেই। এটা ঠিক আপনার খাতায় করা long division-এর মতোই ভাগ করে: shift, compare, subtract। এটাকে বলে restoring division। Setup: dividend রাখুন register Q-তে, divisor রাখুন register M-এ, আর remainder register A-কে 0 করে দিন। তারপর dividend-এর প্রতি bit-এর জন্য একবার করে repeat করুন:

Shift left: (A, Q) জোড়াটাকে এক bit বামে shift করুন — Q-এর top bit ঢুকে যায় A-তে। এটা পরের dividend bit "নামিয়ে আনা", ঠিক খাতার long division-এর মতো।
Subtract: চেষ্টা করুন A = A − M।
Borrow check: result negative না হলে (borrow নেই), divisor "ফিট" করেছে — নতুন quotient bit Q₀ = 1। Result negative হলে (borrow হয়েছে), divisor ফিট করেনি — M যোগ করে A-কে restore করুন, আর Q₀ = 0।

n step-এর পরে (n = bit সংখ্যা), Q-তে quotient আর A-তে remainder থাকে। তাহলে division আসলে বারবার shift-and-subtract-ই — hardware-এর শুধু একটা shifter, একটা subtractor (adder) আর একটা control loop লাগে।

Example:

Divide 13 by 3 in 4-bit binary. Dividend Q = 1101 (13), divisor M = 0011 (3), A = 0000. We run 4 steps (4 bits). "_" is the empty spot where the new quotient bit goes.

Step	After shift left (A, Q)	Try A − M	Borrow?	Action	A	Q
Init	—	—	—	—	0000	1101
1	A = 0001, Q = 101_	0001 − 0011 < 0	Yes	Restore A, Q₀ = 0	0001	1010
2	A = 0011, Q = 010_	0011 − 0011 = 0000	No	Keep A, Q₀ = 1	0000	0101
3	A = 0000, Q = 101_	0000 − 0011 < 0	Yes	Restore A, Q₀ = 0	0000	1010
4	A = 0001, Q = 010_	0001 − 0011 < 0	Yes	Restore A, Q₀ = 0	0001	0100

Result: Q = 0100 = 4 (quotient), A = 0001 = 1 (remainder). Check: $13 = 3 \times 4 + 1$. Correct!

4-bit binary-তে 13 কে 3 দিয়ে ভাগ। Dividend Q = 1101 (13), divisor M = 0011 (3), A = 0000। 4টা step চালাব (4 bit)। "_" হলো খালি জায়গা, যেখানে নতুন quotient bit বসবে।

Step	Shift left-এর পরে (A, Q)	A − M চেষ্টা	Borrow?	Action	A	Q
Init	—	—	—	—	0000	1101
1	A = 0001, Q = 101_	0001 − 0011 < 0	হ্যাঁ	A restore, Q₀ = 0	0001	1010
2	A = 0011, Q = 010_	0011 − 0011 = 0000	না	A রাখো, Q₀ = 1	0000	0101
3	A = 0000, Q = 101_	0000 − 0011 < 0	হ্যাঁ	A restore, Q₀ = 0	0000	1010
4	A = 0001, Q = 010_	0001 − 0011 < 0	হ্যাঁ	A restore, Q₀ = 0	0001	0100

Result: Q = 0100 = 4 (quotient), A = 0001 = 1 (remainder)। Check: $13 = 3 \times 4 + 1$। ঠিক আছে!

Note: Asked October 2017: "How does a computer perform division?" Key words for full marks: align the divisor, then repeat: shift the remainder left, subtract the divisor, quotient bit = 1 if no borrow, else restore (add back) and quotient bit = 0. Practice one full 4-bit trace like the table above — that is exactly what the answer script should show. October 2017-এ এসেছে: "Computer কীভাবে division করে?" Full marks-এর key word: divisor align করো, তারপর repeat: remainder-কে বামে shift, divisor subtract, borrow না হলে quotient bit = 1, নাহলে restore (আবার যোগ) করে quotient bit = 0। উপরের table-এর মতো একটা full 4-bit trace practice করুন — answer script-এ ঠিক এটাই দেখাতে হবে।

3. Pipelining3. Pipelining

Pipelining means overlapping the steps of many instructions, like an assembly line in a factory. While one instruction is being decoded, the next one is already being fetched.

Assembly-line analogy: think of a laundry with 3 machines: washer, dryer, iron. If each load takes 1 hour per machine, doing 4 loads one-by-one takes 12 hours. But if you start washing load 2 while load 1 is drying, all 4 loads finish in only 6 hours. Same machines, smarter timing.

The classic 5-stage pipeline

IF — Instruction Fetch: get the instruction from memory.
ID — Instruction Decode: decode it and read registers.
EX — Execute: ALU does the operation (or computes an address).
MEM — Memory access: read/write data memory if needed.
WB — Write Back: write the result into a register.

Pipelining মানে অনেকগুলো instruction-এর step overlap করা, ঠিক factory-র assembly line-এর মতো। একটা instruction যখন decode হচ্ছে, তখনই পরেরটা fetch হয়ে যাচ্ছে।

Assembly-line analogy: ভাবুন একটা laundry-তে 3টা machine আছে: washer, dryer, iron। প্রতি machine-এ এক load-এ 1 ঘণ্টা লাগলে, 4 load এক এক করে করলে 12 ঘণ্টা লাগবে। কিন্তু load 1 যখন dry হচ্ছে তখনই load 2 wash শুরু করলে, 4 load শেষ হয় মাত্র 6 ঘণ্টায়। Machine একই, timing-টা smart।

Classic 5-stage pipeline

IF — Instruction Fetch: memory থেকে instruction আনা।
ID — Instruction Decode: decode করা আর register read করা।
EX — Execute: ALU operation করে (বা address হিসাব করে)।
MEM — Memory access: দরকার হলে data memory read/write।
WB — Write Back: result register-এ লেখা।

Pipeline timing diagram: 5 instructions finish in 9 cycles instead of 25.Pipeline timing diagram: 5টা instruction 25 cycle-এর বদলে 9 cycle-এ শেষ।

Speedup formula (BUET favorite)

Say the pipeline has $k$ stages, each stage takes one cycle of time $t$, and we run $n$ instructions.

Without pipeline: $T_{\text{non-pipe}} = n \cdot k \cdot t$
With pipeline: the first instruction takes $k$ cycles, then one instruction finishes every cycle: $T_{\text{pipe}} = (k + n - 1) \cdot t$

Speedup formula (BUET-এর favorite)

ধরি pipeline-এ $k$ টা stage আছে, প্রতি stage-এ এক cycle সময় $t$ লাগে, আর আমরা $n$ টা instruction চালাই।

Pipeline ছাড়া: $T_{\text{non-pipe}} = n \cdot k \cdot t$
Pipeline সহ: প্রথম instruction-এ $k$ cycle লাগে, তারপর প্রতি cycle-এ একটা instruction শেষ হয়: $T_{\text{pipe}} = (k + n - 1) \cdot t$

\[ \text{Speedup} = \frac{T_{\text{non-pipe}}}{T_{\text{pipe}}} = \frac{n \cdot k}{k + n - 1} \]

Example:

A 5-stage pipeline, clock cycle $t = 2$ ns, runs 100 instructions.

Non-pipelined time: $100 \times 5 \times 2 = 1000$ ns.
Pipelined time: $(5 + 100 - 1) \times 2 = 104 \times 2 = 208$ ns.
Speedup: $1000 / 208 \approx 4.8$.

Notice: speedup is close to 5 (the number of stages) but never reaches it. As $n \to \infty$, speedup $\to k$.

একটা 5-stage pipeline, clock cycle $t = 2$ ns, 100টা instruction চালায়।

Pipeline ছাড়া সময়: $100 \times 5 \times 2 = 1000$ ns।
Pipeline সহ সময়: $(5 + 100 - 1) \times 2 = 104 \times 2 = 208$ ns।
Speedup: $1000 / 208 \approx 4.8$।

খেয়াল করুন: speedup প্রায় 5-এর (stage সংখ্যার) কাছাকাছি, কিন্তু কখনো 5 হয় না। $n \to \infty$ হলে speedup $\to k$।

Note: Memorize the pattern: pipelined cycles = $k + (n-1)$, speedup = $\dfrac{nk}{k+n-1}$, and maximum (ideal) speedup = $k$. Almost every architecture exam has one question built on this. Pattern-টা মুখস্থ রাখুন: pipelined cycle = $k + (n-1)$, speedup = $\dfrac{nk}{k+n-1}$, আর maximum (ideal) speedup = $k$। প্রায় প্রতিটা architecture exam-এ এটার উপর একটা প্রশ্ন থাকে।

Pipeline hazards

A hazard is anything that stops the pipeline from finishing one instruction every cycle. Three kinds:

Structural hazard: two instructions need the same hardware at the same time. Example: one instruction fetching from memory while another reads data from the same single memory. Fix: separate instruction/data caches, or duplicate hardware.
Data hazard: an instruction needs a result that is not ready yet. Example:
```
ADD R1, R2, R3   ; R1 = R2 + R3
SUB R4, R1, R5   ; needs R1 — but R1 is written in WB, much later!
```
This is a RAW (Read After Write) hazard — the most common one.
Control hazard: a branch (jump) changes the PC, but the pipeline already fetched the wrong next instructions. Those must be thrown away (flushed).

Fixes: forwarding, stalls, branch prediction

Forwarding (bypassing): send the ALU result directly from the EX stage output to the next instruction's EX input, without waiting for WB. Removes most data-hazard delays.
Stall (bubble): if forwarding is not enough (e.g., value comes from a memory LOAD), the pipeline inserts empty cycles. Each stall adds one cycle to total time.
Branch prediction: the CPU guesses which way the branch will go and keeps fetching along that guess. Right guess → no time lost. Wrong guess → flush and restart from the correct place. Modern CPUs guess correctly over 90% of the time.

Pipeline hazard

Hazard হলো এমন কিছু যা pipeline-কে প্রতি cycle-এ একটা instruction শেষ করা থেকে আটকায়। তিন ধরনের:

Structural hazard: দুইটা instruction-এর একই সময়ে একই hardware দরকার। Example: একটা instruction memory থেকে fetch হচ্ছে, আর আরেকটা একই single memory থেকে data পড়ছে। সমাধান: আলাদা instruction/data cache, বা hardware duplicate করা।
Data hazard: একটা instruction-এর এমন result দরকার যা এখনো ready না। Example:
```
ADD R1, R2, R3   ; R1 = R2 + R3
SUB R4, R1, R5   ; R1 দরকার — কিন্তু R1 লেখা হয় WB-তে, অনেক পরে!
```
এটা RAW (Read After Write) hazard — সবচেয়ে common।
Control hazard: branch (jump) PC বদলে দেয়, কিন্তু pipeline ততক্ষণে ভুল instruction fetch করে ফেলেছে। সেগুলো ফেলে দিতে হয় (flush)।

সমাধান: forwarding, stall, branch prediction

Forwarding (bypassing): ALU-র result EX stage-এর output থেকে সরাসরি পরের instruction-এর EX input-এ পাঠানো, WB-এর জন্য wait না করে। বেশিরভাগ data-hazard delay দূর হয়।
Stall (bubble): forwarding-ও যথেষ্ট না হলে (যেমন value আসছে memory LOAD থেকে), pipeline খালি cycle ঢোকায়। প্রতিটা stall মোট সময়ে এক cycle যোগ করে।
Branch prediction: CPU আন্দাজ করে branch কোন দিকে যাবে, আর সেই আন্দাজ ধরেই fetch চালিয়ে যায়। আন্দাজ ঠিক হলে → সময় নষ্ট নেই। ভুল হলে → flush করে ঠিক জায়গা থেকে আবার শুরু। আধুনিক CPU 90%-এর বেশি সময় ঠিক আন্দাজ করে।

Note: Quick ID trick for exams: same hardware needed twice → structural; result not ready → data; branch/jump involved → control. Exam-এর quick ID trick: একই hardware দুইবার দরকার → structural; result ready না → data; branch/jump জড়িত → control।

Superscalar Processor (Definition Box)

Definition: a superscalar processor can issue (start) more than one instruction in the same clock cycle. It does this with duplicate functional units — two or more ALUs, separate load/store and floating-point units — plus hardware that picks independent instructions to run together.

Scalar pipelined CPU: stages overlap, but at most 1 instruction finishes per cycle (best CPI = 1).
Superscalar CPU: like several pipelines running side by side — 2 or more instructions can finish per cycle (CPI < 1). A "2-way superscalar" issues up to 2 per cycle.

One-line comparison: pipelining overlaps the stages of instructions; superscalar adds extra hardware so multiple instructions go through those stages at the same time.

Real-chip example (a BUET favorite): the Intel Pentium (1993) has two integer pipelines, called the U pipe and the V pipe. If two neighboring instructions are simple and independent, the Pentium sends one to U and one to V in the same cycle — so it can complete 2 instructions per cycle. That is exactly the definition of superscalar. The older 80386 has only one pipeline, so it can never start more than 1 instruction per cycle — it is a plain scalar processor.

Superscalar Processor (Definition Box)

Definition: superscalar processor একই clock cycle-এ একাধিক instruction issue (শুরু) করতে পারে। এজন্য এতে duplicate functional unit থাকে — দুই বা তার বেশি ALU, আলাদা load/store আর floating-point unit — সাথে এমন hardware যা independent instruction বেছে নিয়ে একসাথে চালায়।

Scalar pipelined CPU: stage overlap হয়, কিন্তু প্রতি cycle-এ সর্বোচ্চ 1টা instruction শেষ হয় (best CPI = 1)।
Superscalar CPU: যেন কয়েকটা pipeline পাশাপাশি চলছে — প্রতি cycle-এ 2 বা তার বেশি instruction শেষ হতে পারে (CPI < 1)। "2-way superscalar" মানে প্রতি cycle-এ 2টা পর্যন্ত issue।

One-line comparison: pipelining instruction-এর stage-গুলো overlap করে; superscalar বাড়তি hardware দিয়ে একাধিক instruction-কে একই সময়ে সেই stage-গুলোর ভেতর দিয়ে চালায়।

Real-chip example (BUET-এর প্রিয়): Intel Pentium-এ (1993) দুইটা integer pipeline আছে — U pipe আর V pipe। পাশাপাশি দুইটা instruction simple আর independent হলে Pentium একই cycle-এ একটাকে U-তে আর একটাকে V-তে পাঠায় — তাই এটা প্রতি cycle-এ 2টা instruction শেষ করতে পারে। এটাই ঠিক superscalar-এর definition। পুরানো 80386-এ pipeline মাত্র একটা, তাই প্রতি cycle-এ 1টার বেশি instruction কখনোই শুরু করতে পারে না — এটা সাধারণ scalar processor।

Note: Asked April 2017: "What is a superscalar microprocessor?" Asked October 2017: "Why is the Pentium called superscalar but the 80386 is not?" Answer with the U/V pipe fact above: Pentium = 2 pipelines → 2 instructions/cycle → superscalar; 80386 = 1 pipeline → scalar. Modern CPUs (Intel Core, ARM Cortex-A) are all superscalar — typically 4–8 instructions issued per cycle. April 2017-এ এসেছে: "What is a superscalar microprocessor?" October 2017-এ এসেছে: "Pentium-কে superscalar বলা হয় কিন্তু 80386-কে না কেন?" উত্তরে উপরের U/V pipe fact-টা লিখুন: Pentium = 2 pipeline → প্রতি cycle-এ 2 instruction → superscalar; 80386 = 1 pipeline → scalar। আধুনিক CPU (Intel Core, ARM Cortex-A) সবই superscalar — সাধারণত প্রতি cycle-এ 4–8টা instruction issue হয়।

4. Cache & Memory Hierarchy4. Cache & Memory Hierarchy

Fast memory is expensive and small. Big memory is cheap and slow. So computers use a hierarchy: a small fast layer on top, bigger slower layers below. The goal: feel as fast as the top layer, but as big as the bottom layer.

Fast memory দামি আর ছোট। বড় memory সস্তা কিন্তু slow। তাই computer একটা hierarchy use করে: উপরে ছোট fast layer, নিচে বড় slow layer। লক্ষ্য: speed-এ উপরের layer-এর মতো, size-এ নিচের layer-এর মতো মনে হওয়া।

Memory hierarchy pyramid from registers at top to tape at bottom — Memory hierarchy pyramid: going down = bigger, slower, cheaper per byte.Memory hierarchy pyramid: নিচে নামলে = বড়, slow, per byte সস্তা।

LevelLevel	Typical sizeTypical size	Typical speedTypical speed	Cost per bytePer byte cost
Registers	~1 KB	< 1 ns	Highestসবচেয়ে বেশি
Cache (SRAM)	KB – MB	1 – 10 ns	Highবেশি
Main memory / RAM (DRAM)	GB	50 – 100 ns	Mediumমাঝারি
SSD	Hundreds of GBশত শত GB	~100 µs	Lowকম
HDD	TB	~10 ms	Lowestসবচেয়ে কম

Why cache works: locality of reference

Programs do not touch memory randomly. They show locality:

Temporal locality: if you used an address recently, you will likely use it again soon. Example: a loop runs the same instructions many times.
Spatial locality: if you used an address, you will likely use its neighbors next. Example: reading an array element by element.

Because of locality, keeping recently used blocks in a small fast cache catches most accesses.

Hit and miss

Cache hit: the data is in the cache. Fast.
Cache miss: not in cache; must fetch the whole block from main memory (the miss penalty). Slow.
Hit ratio = hits ÷ total accesses.

Cache কেন কাজ করে: locality of reference

Program এলোমেলোভাবে memory touch করে না। এদের মধ্যে locality থাকে:

Temporal locality: কোনো address সম্প্রতি use করলে, শিগগিরই আবার use করার সম্ভাবনা বেশি। Example: loop একই instruction বারবার চালায়।
Spatial locality: কোনো address use করলে, এর পাশেরগুলো পরে use করার সম্ভাবনা বেশি। Example: array element এক এক করে পড়া।

এই locality-র কারণেই সম্প্রতি use করা block ছোট fast cache-এ রাখলে বেশিরভাগ access সেখানেই পাওয়া যায়।

Hit আর miss

Cache hit: data cache-এ আছে। Fast।
Cache miss: cache-এ নেই; পুরো block main memory থেকে আনতে হয় (এটাই miss penalty)। Slow।
Hit ratio = hit ÷ মোট access।

Cache mapping: where does a memory block go?

Memory is split into blocks; cache is split into lines of the same size. Mapping decides which line a block may use:

Direct mapping: each block has exactly ONE possible line: line = block number mod number of lines. Simple and fast, but two hot blocks may fight for the same line.
Fully associative: a block can go in ANY line. Most flexible, but needs to compare all tags at once — costly hardware.
Set-associative: the compromise. Lines are grouped into sets; a block maps to one set, but can sit in any line of that set. "4-way" means 4 lines per set.

The CPU splits every address into three fields:

Cache mapping: memory block কোথায় যাবে?

Memory ভাগ হয় block-এ; cache ভাগ হয় একই size-এর line-এ। Mapping ঠিক করে কোন block কোন line-এ যেতে পারবে:

Direct mapping: প্রতিটা block-এর জন্য ঠিক একটাই সম্ভব line: line = block number mod line সংখ্যা। Simple আর fast, কিন্তু দুইটা দরকারি block একই line-এর জন্য মারামারি করতে পারে।
Fully associative: block যেকোনো line-এ যেতে পারে। সবচেয়ে flexible, কিন্তু সব tag একসাথে compare করতে হয় — hardware খরচ বেশি।
Set-associative: মাঝামাঝি সমাধান। Line-গুলো set-এ ভাগ করা; একটা block একটা নির্দিষ্ট set-এ map হয়, কিন্তু সেই set-এর যেকোনো line-এ বসতে পারে। "4-way" মানে প্রতি set-এ 4টা line।

CPU প্রতিটা address-কে তিন ভাগে ভাঙে:

|   tag   |  index  | offset |
   who?     which      which
            line/set?  byte in block?

\[ \text{offset bits} = \log_2(\text{block size}), \quad \text{index bits} = \log_2(\text{number of lines or sets}), \quad \text{tag} = \text{rest} \]

Example:

Address breakdown (direct mapping) — a must-practice problem. A direct-mapped cache is 64 KB with 16-byte blocks. Addresses are 32 bits. Find tag, index, offset bits.

Number of lines = cache size ÷ block size = $64\text{ KB} / 16\text{ B} = 2^{16}/2^4 = 2^{12} = 4096$ lines.
Offset bits = $\log_2 16 = 4$.
Index bits = $\log_2 4096 = 12$.
Tag bits = $32 - 12 - 4 = 16$.

So address = [ 16-bit tag | 12-bit index | 4-bit offset ].

Set-associative version: make it 4-way. Sets = $4096 / 4 = 1024 = 2^{10}$. Now index = 10 bits, offset = 4 bits, tag = $32-10-4 = 18$ bits.

Address breakdown (direct mapping) — অবশ্যই practice করার মতো প্রশ্ন। একটা direct-mapped cache 64 KB, block 16 byte। Address 32 bit। Tag, index, offset bit বের করুন।

Line সংখ্যা = cache size ÷ block size = $64\text{ KB} / 16\text{ B} = 2^{16}/2^4 = 2^{12} = 4096$ টা line।
Offset bit = $\log_2 16 = 4$।
Index bit = $\log_2 4096 = 12$।
Tag bit = $32 - 12 - 4 = 16$।

তাহলে address = [ 16-bit tag | 12-bit index | 4-bit offset ]।

Set-associative version: এটাকে 4-way করি। Set = $4096 / 4 = 1024 = 2^{10}$। এখন index = 10 bit, offset = 4 bit, tag = $32-10-4 = 18$ bit।

Note: Direct mapping exam shortcut: line number = block number mod (number of lines). Example: block 12 in an 8-line cache goes to line $12 \bmod 8 = 4$. Blocks 4, 12, 20, 28... all fight for line 4. Direct mapping-এর exam shortcut: line number = block number mod (line সংখ্যা)। Example: 8-line cache-এ block 12 যাবে line $12 \bmod 8 = 4$-এ। Block 4, 12, 20, 28... সবাই line 4-এর জন্য fight করে।

Average Memory Access Time (AMAT)

How fast does memory feel on average?

Average Memory Access Time (AMAT)

গড়ে memory কত fast মনে হয়?

\[ \text{AMAT} = \text{hit time} + \text{miss rate} \times \text{miss penalty} \]

Example:

Cache hit time = 1 ns, miss rate = 5%, miss penalty (going to main memory) = 100 ns.

$ \text{AMAT} = 1 + 0.05 \times 100 = 1 + 5 = 6 \text{ ns} $

Even with 95% hits, misses add 5 ns on average — misses are expensive! With two levels: L1 hit 1 ns, L1 miss rate 10%, L2 hit 10 ns, L2 miss rate 20%, memory 100 ns:

$ \text{AMAT} = 1 + 0.10 \times (10 + 0.20 \times 100) = 1 + 0.10 \times 30 = 4 \text{ ns} $

Cache hit time = 1 ns, miss rate = 5%, miss penalty (main memory-তে যাওয়া) = 100 ns।

$ \text{AMAT} = 1 + 0.05 \times 100 = 1 + 5 = 6 \text{ ns} $

95% hit হওয়ার পরেও miss গড়ে 5 ns যোগ করে — miss অনেক দামি! দুই level হলে: L1 hit 1 ns, L1 miss rate 10%, L2 hit 10 ns, L2 miss rate 20%, memory 100 ns:

$ \text{AMAT} = 1 + 0.10 \times (10 + 0.20 \times 100) = 1 + 0.10 \times 30 = 4 \text{ ns} $

Write policies

Write-through: write to cache AND main memory at the same time. Memory always up-to-date, but slower writes.
Write-back: write only to cache; mark the line "dirty". Write to memory later, only when the line is replaced. Faster, but memory can be stale for a while.

Replacement policies (briefly)

When a set is full, which line do we evict? LRU (Least Recently Used — evict the one unused for longest, best for locality), FIFO (evict the oldest), Random (cheap to build). Direct mapping needs no policy — there is only one choice.

Cache levels

L1: smallest (32–64 KB), fastest, inside each core; usually split into instruction-cache and data-cache.
L2: bigger (256 KB – 1 MB), a bit slower, per core.
L3: biggest (several MB), slowest of the three, shared by all cores.

A miss in L1 tries L2, then L3, then main memory.

Write policy

Write-through: cache আর main memory-তে একসাথে লেখা। Memory সবসময় up-to-date, কিন্তু write slow।
Write-back: শুধু cache-এ লেখা; line-টা "dirty" mark করা। Memory-তে লেখা হয় পরে, line replace হওয়ার সময়। Fast, কিন্তু memory কিছু সময় stale থাকতে পারে।

Replacement policy (সংক্ষেপে)

Set ভরে গেলে কোন line ফেলব? LRU (Least Recently Used — সবচেয়ে বেশিদিন use না হওয়াটা ফেলা, locality-র জন্য best), FIFO (সবচেয়ে পুরানোটা ফেলা), Random (বানানো সস্তা)। Direct mapping-এ policy লাগে না — choice একটাই।

Cache level

L1: সবচেয়ে ছোট (32–64 KB), সবচেয়ে fast, প্রতিটা core-এর ভেতরে; সাধারণত instruction-cache আর data-cache আলাদা।
L2: বড় (256 KB – 1 MB), একটু slow, per core।
L3: সবচেয়ে বড় (কয়েক MB), তিনটার মধ্যে slow, সব core মিলে share করে।

L1-এ miss হলে L2, তারপর L3, তারপর main memory চেষ্টা হয়।

Write-through vs write-back at a glance:

Write-through vs write-back এক নজরে:

PointPoint	Write-through	Write-back
When memory is writtenMemory-তে কখন লেখা হয়	Immediately, on every writeসাথে সাথে, প্রতিটা write-এ	Later, only when the line is evictedপরে, শুধু line evict হওয়ার সময়
Bus/memory trafficBus/memory traffic	High (every write goes to memory)বেশি (প্রতিটা write memory-তে যায়)	Low (many writes stay in cache)কম (অনেক write cache-এই থেকে যায়)
Dirty bit needed?Dirty bit লাগে?	Noনা	Yes — marks lines changed but not yet savedহ্যাঁ — বদলানো কিন্তু save না হওয়া line mark করে
Memory consistencyMemory consistency	Memory always up-to-date (simple, safe)Memory সবসময় up-to-date (simple, safe)	Memory can be stale until write-back happensWrite-back না হওয়া পর্যন্ত memory stale থাকতে পারে
Write speedWrite speed	Slower (waits for memory, unless a write buffer helps)Slow (memory-র জন্য অপেক্ষা, write buffer না থাকলে)	Faster (cache speed only)Fast (শুধু cache speed)
Good forকোথায় ভালো	Simple systems, I/O/DMA sharing memory, easy multi-core coherenceSimple system, memory share করা I/O/DMA, সহজ multi-core coherence	Performance-focused CPUs — most modern caches use itPerformance-focused CPU — বেশিরভাগ আধুনিক cache এটাই use করে

Note: Asked October 2017: "Explain write-through and write-back cache policies. Which one is better and why?" Safe answer: write-back is usually better for performance (less memory traffic, faster writes, needs a dirty bit); write-through is simpler and keeps memory always consistent. Give both sides — the table above is the full answer. October 2017-এ এসেছে: "Write-through আর write-back cache policy ব্যাখ্যা করো। কোনটা better আর কেন?" Safe answer: performance-এর জন্য সাধারণত write-back better (memory traffic কম, write fast, dirty bit লাগে); write-through simple আর memory সবসময় consistent রাখে। দুই দিকই লিখুন — উপরের table-টাই full answer।

Note: L1 being split into instruction + data cache is a small Harvard architecture inside a Von Neumann machine — a favorite viva question. L1-কে instruction + data cache-এ ভাগ করা মানে Von Neumann machine-এর ভেতরে একটা ছোট Harvard architecture — viva-র প্রিয় প্রশ্ন।

Memory Interleaving (Banking)

DRAM is slow: once an access starts, the chip stays busy for the whole access time. Trick: split main memory into $N$ independent banks and spread consecutive addresses across them — address $i$ goes to bank $i \bmod N$. Now sequential accesses (reading an array, fetching instructions) land in different banks, so they can overlap: while bank 0 is still busy, the CPU already starts bank 1, then bank 2... It is pipelining, but for memory. Best case, bandwidth grows by a factor of $N$.

Memory Interleaving (Banking)

DRAM slow: একটা access শুরু হলে পুরো access time ধরে chip busy থাকে। Trick: main memory-কে $N$টা independent bank-এ ভাগ করা আর পরপর address-গুলো এদের মধ্যে ছড়িয়ে দেওয়া — address $i$ যায় bank $i \bmod N$-এ। এখন sequential access (array পড়া, instruction fetch) আলাদা আলাদা bank-এ পড়ে, তাই এরা overlap করতে পারে: bank 0 busy থাকতেই CPU bank 1 শুরু করে দেয়, তারপর bank 2... এটা আসলে memory-র জন্য pipelining। Best case-এ bandwidth $N$ গুণ বাড়ে।

Address:  0    1    2    3    4    5    6    7   ...
Bank:     B0   B1   B2   B3   B0   B1   B2   B3  ...
          (4-way interleaving: address i → bank i mod 4)

Example:

4 banks, each with access time 60 ns. Read 4 consecutive words.

No interleaving (1 bank): accesses go one by one: $4 \times 60 = 240$ ns. Throughput = 1 word per 60 ns.
4-way interleaved: the 4 words sit in 4 different banks, so all 4 accesses run overlapped (started one right after another). All 4 words arrive in about 60 ns (plus a tiny startup). Effective time per word ≈ $60/4 = 15$ ns → 4× bandwidth.

4টা bank, প্রতিটার access time 60 ns। পরপর 4টা word পড়তে হবে।

Interleaving ছাড়া (1 bank): access-গুলো এক এক করে: $4 \times 60 = 240$ ns। Throughput = প্রতি 60 ns-এ 1 word।
4-way interleaved: 4টা word 4টা আলাদা bank-এ, তাই 4টা access-ই overlap করে চলে (এক এক করে ঠিক পরপর start করা)। 4টা word-ই আসে প্রায় 60 ns-এ (সামান্য startup সহ)। Effective time per word ≈ $60/4 = 15$ ns → 4× bandwidth।

Note: Asked April 2019: "How does memory interleaving/banking improve bandwidth?" Key words for full marks: consecutive addresses in different banks → accesses overlap → up to $N\times$ bandwidth with $N$ banks. Bonus link: this is why DDR RAM chips have multiple internal banks, and why dual-channel RAM is faster. April 2019-এ এসেছে: "Memory interleaving/banking কীভাবে bandwidth বাড়ায়?" Full marks-এর key word: পরপর address আলাদা bank-এ → access overlap করে → $N$টা bank-এ সর্বোচ্চ $N\times$ bandwidth। Bonus link: এজন্যই DDR RAM chip-এ একাধিক internal bank থাকে, আর dual-channel RAM faster।

5. I/O Organization5. I/O Organization

I/O devices (keyboard, disk, network card) are millions of times slower than the CPU. The question: how should the CPU talk to them without wasting time? Three ways.

Programmed I/O (polling): the CPU keeps asking the device "are you ready?" in a loop. Simple, but the CPU wastes almost all its time waiting.
Interrupt-driven I/O: the CPU starts the device and goes back to other work. When the device is ready, it sends an interrupt signal, and the CPU handles it. Much better — but the CPU still moves every byte itself.
DMA (Direct Memory Access): a special DMA controller moves whole blocks of data between device and memory by itself. The CPU only says "transfer this block", then gets ONE interrupt when everything is done. Best for large transfers (disk, network).

I/O device (keyboard, disk, network card) CPU-এর চেয়ে লাখো গুণ slow। প্রশ্ন হলো: CPU সময় নষ্ট না করে এদের সাথে কথা বলবে কীভাবে? তিনটা উপায়।

Programmed I/O (polling): CPU loop-এ ঘুরে ঘুরে device-কে জিজ্ঞেস করে "ready তো?" Simple, কিন্তু CPU-র প্রায় সব সময় wait-এই নষ্ট হয়।
Interrupt-driven I/O: CPU device চালু করে দিয়ে অন্য কাজে চলে যায়। Device ready হলে interrupt signal পাঠায়, তখন CPU সেটা handle করে। অনেক ভালো — কিন্তু প্রতিটা byte এখনো CPU নিজেই সরায়।
DMA (Direct Memory Access): আলাদা একটা DMA controller device আর memory-র মধ্যে পুরো block data নিজে নিজেই সরায়। CPU শুধু বলে "এই block transfer করো", তারপর সব শেষ হলে মাত্র একটা interrupt পায়। বড় transfer-এর (disk, network) জন্য best।

PointPoint	Programmed I/O	Interrupt-driven I/O	DMA
Who checks readiness?Ready কে check করে?	CPU, in a busy loopCPU, busy loop-এ	Device signals CPUDevice CPU-কে signal দেয়	DMA controller handles itDMA controller-ই সামলায়
Who moves the data?Data কে সরায়?	CPU	CPU	DMA controllerDMA controller
CPU time wastedCPU-র সময় নষ্ট	Very highখুব বেশি	Medium (one interrupt per byte/word)মাঝারি (প্রতি byte/word-এ এক interrupt)	Almost none (one interrupt per block)প্রায় নেই (প্রতি block-এ এক interrupt)
Best forকীসের জন্য ভালো	Very simple/slow devicesখুব simple/slow device	Keyboard, mouseKeyboard, mouse	Disk, network — big blocksDisk, network — বড় block

Interrupt handling steps

Device raises an interrupt signal.
CPU finishes the current instruction (never stops mid-instruction).
CPU saves its state: PC and status flags go onto the stack.
CPU finds the address of the correct ISR (Interrupt Service Routine) from the interrupt vector table — a table in memory where entry $i$ holds the ISR address for interrupt number $i$.
CPU jumps to the ISR and runs it.
ISR ends with a "return from interrupt" instruction; saved PC and flags are restored.
The original program continues as if nothing happened.

Memory-mapped vs isolated I/O

Memory-mapped I/O: device registers get addresses inside the normal memory address space. Any memory instruction (LOAD/STORE) can talk to devices. Simple, but eats memory addresses. Used by ARM.
Isolated (port-mapped) I/O: devices live in a separate small address space with special instructions (IN, OUT). Memory space stays full-size, but you need extra instructions. Used by Intel x86.

Interrupt handle করার step

Device একটা interrupt signal তোলে।
CPU চলতি instruction-টা শেষ করে (instruction-এর মাঝখানে কখনো থামে না)।
CPU নিজের state save করে: PC আর status flag stack-এ যায়।
CPU সঠিক ISR-এর (Interrupt Service Routine) address খুঁজে নেয় interrupt vector table থেকে — memory-র একটা table, যার entry $i$-তে interrupt number $i$-এর ISR address থাকে।
CPU ISR-এ jump করে সেটা চালায়।
ISR শেষ হয় "return from interrupt" instruction দিয়ে; save করা PC আর flag ফেরত আসে।
আগের program এমনভাবে চলতে থাকে যেন কিছুই হয়নি।

Memory-mapped vs isolated I/O

Memory-mapped I/O: device-এর register সাধারণ memory address space-এর ভেতরেই address পায়। যেকোনো memory instruction (LOAD/STORE) দিয়ে device-এর সাথে কথা বলা যায়। Simple, কিন্তু memory address খেয়ে ফেলে। ARM এটা use করে।
Isolated (port-mapped) I/O: device থাকে আলাদা ছোট address space-এ, special instruction (IN, OUT) দিয়ে access হয়। Memory space পুরোটা থাকে, কিন্তু বাড়তি instruction লাগে। Intel x86 এটা use করে।

Note: One-line exam answer for "why DMA?": DMA frees the CPU — data moves between device and memory without the CPU touching every byte, and the CPU gets only one interrupt per block. "কেন DMA?"-এর one-line exam answer: DMA CPU-কে free করে দেয় — data device আর memory-র মধ্যে যায় CPU-কে প্রতিটা byte touch করতে না দিয়েই, আর CPU প্রতি block-এ মাত্র একটা interrupt পায়।

6. Microprocessors & Microcontrollers6. Microprocessors & Microcontrollers

Both are "computers on a chip", but they are built for different jobs.

Microprocessor: just the CPU on one chip. Memory, storage, and I/O are separate chips outside. Built for general-purpose power. Example: Intel Core i7, AMD Ryzen.
Microcontroller (MCU): a whole tiny computer on one chip — CPU + RAM + flash (program memory) + I/O peripherals, all inside. Built for controlling one specific device cheaply and with low power. Example: ATmega328P (the Arduino chip), STM32, PIC.

দুটোই "এক chip-এ computer", কিন্তু কাজ আলাদা।

Microprocessor: এক chip-এ শুধু CPU। Memory, storage, I/O বাইরের আলাদা chip-এ। General-purpose power-এর জন্য তৈরি। Example: Intel Core i7, AMD Ryzen।
Microcontroller (MCU): এক chip-এই পুরো ছোট computer — CPU + RAM + flash (program memory) + I/O peripheral, সব ভেতরে। কম দামে, কম power-এ একটা নির্দিষ্ট device control করার জন্য তৈরি। Example: ATmega328P (Arduino-র chip), STM32, PIC।

PointPoint	Microprocessor	Microcontroller
What is on the chipChip-এ কী থাকে	Only CPUশুধু CPU	CPU + RAM + flash + I/OCPU + RAM + flash + I/O
Purposeউদ্দেশ্য	General computingGeneral computing	Control one specific taskনির্দিষ্ট একটা কাজ control করা
SpeedSpeed	GHz rangeGHz range	Usually MHz rangeসাধারণত MHz range
Power usePower খরচ	Tens of wattsদশ-বিশ watt	Milliwatts (runs on battery)Milliwatt (battery-তেই চলে)
Costদাম	Highবেশি	Very low (often < $1)খুব কম (প্রায়ই < $1)
Architecture (typical)Architecture (সাধারণত)	Von Neumann styleVon Neumann style	Often Harvard styleপ্রায়ই Harvard style
Used inকোথায় use হয়	PC, laptop, serverPC, laptop, server	Washing machine, car ECU, drone, IoT sensorWashing machine, গাড়ির ECU, drone, IoT sensor

The Intel 8086 in brief

The 8086 (1978) is the grandfather of today's x86 PCs. Exams like its basic facts:

16-bit microprocessor: 16-bit registers and 16-bit data bus.
20-bit address bus → $2^{20}$ = 1 MB memory.
General registers: AX (accumulator), BX (base), CX (counter), DX (data). Each splits into high/low bytes: AX = AH + AL.
Pointer/index registers: SP (stack pointer), BP (base pointer), SI (source index), DI (destination index), and IP (instruction pointer — the 8086 name for PC).
Segment registers: CS (code), DS (data), SS (stack), ES (extra).

Segmentation idea: registers are 16-bit but addresses are 20-bit. Trick: a 20-bit physical address is built from two 16-bit values:

সংক্ষেপে Intel 8086

8086 (1978) হলো আজকের x86 PC-গুলোর দাদা। Exam-এ এর basic fact-গুলো আসে:

16-bit microprocessor: 16-bit register আর 16-bit data bus।
20-bit address bus → $2^{20}$ = 1 MB memory।
General register: AX (accumulator), BX (base), CX (counter), DX (data)। প্রতিটা high/low byte-এ ভাগ হয়: AX = AH + AL।
Pointer/index register: SP (stack pointer), BP (base pointer), SI (source index), DI (destination index), আর IP (instruction pointer — PC-র 8086 নাম)।
Segment register: CS (code), DS (data), SS (stack), ES (extra)।

Segmentation-এর idea: register 16-bit কিন্তু address 20-bit। Trick: দুইটা 16-bit value থেকে 20-bit physical address বানানো হয়:

\[ \text{Physical address} = \text{Segment} \times 16 + \text{Offset} \]

Example:

CS = 1000H and IP = 0200H. Physical address of the next instruction?

$ 1000\text{H} \times 10\text{H} + 0200\text{H} = 10000\text{H} + 0200\text{H} = \mathbf{10200H} $

(Multiplying by 16 in hex just appends one zero.)

CS = 1000H আর IP = 0200H। পরের instruction-এর physical address কত?

$ 1000\text{H} \times 10\text{H} + 0200\text{H} = 10000\text{H} + 0200\text{H} = \mathbf{10200H} $

(Hex-এ 16 দিয়ে গুণ মানে শুধু একটা শূন্য বসানো।)

8085 vs 8086 in brief

The 8085 came before the 8086. A quick side-by-side:

সংক্ষেপে 8085 vs 8086

8086-এর আগে এসেছিল 8085। Quick side-by-side:

PointPoint	8085	8086
Word sizeWord size	8-bit CPU, 8-bit data bus8-bit CPU, 8-bit data bus	16-bit CPU, 16-bit data bus16-bit CPU, 16-bit data bus
Address bus / memoryAddress bus / memory	16-bit → 2¹⁶ = 64 KB16-bit → 2¹⁶ = 64 KB	20-bit → 2²⁰ = 1 MB20-bit → 2²⁰ = 1 MB
SegmentationSegmentation	None — one flat 64 KB spaceনেই — একটাই flat 64 KB space	Yes — CS/DS/SS/ES; address = segment × 16 + offsetআছে — CS/DS/SS/ES; address = segment × 16 + offset
PipeliningPipelining	No — fetch then execute, one at a timeনেই — fetch তারপর execute, একটা একটা করে	Simple: 6-byte prefetch queue (BIU fetches while EU executes)Simple: 6-byte prefetch queue (EU execute করার সময় BIU fetch করে)

Note: Asked October 2018: "Differentiate between 8085 and 8086." The three must-write points: 8 vs 16 bit, 64 KB vs 1 MB address space, and only the 8086 has segmentation (segment × 16 + offset). October 2018-এ এসেছে: "8085 আর 8086-এর পার্থক্য লেখো।" যে তিনটা point অবশ্যই লিখবেন: 8 vs 16 bit, 64 KB vs 1 MB address space, আর segmentation (segment × 16 + offset) শুধু 8086-এ আছে।

Common microcontroller parts (peripherals)

GPIO (General Purpose Input/Output): pins you control from code — read a button, light an LED.
Timers/Counters: count clock ticks; used for delays, measuring time, and PWM (motor speed, LED dimming).
ADC (Analog-to-Digital Converter): turns an analog voltage (temperature sensor, light sensor) into a number.
UART: simple serial communication, two wires (TX/RX) — how Arduino talks to your PC. Related: SPI and I2C for talking to other chips.
Flash / EEPROM: non-volatile memory holding the program and saved settings.

Where each is used

Microprocessor: your PC, laptop, phone application processor, servers — anywhere you run many different big programs.
Microcontroller: embedded systems — washing machine, microwave, car engine control (ECU), TV remote, smart bulb, drone flight controller, IoT sensors. A modern car has dozens of MCUs.
Arduino: a beginner-friendly board built around the AVR ATmega328P microcontroller (8-bit, 16 MHz, 2 KB RAM, 32 KB flash, Harvard architecture). Great proof that an MCU needs almost nothing around it to work.

Microcontroller-এর common অংশ (peripheral)

GPIO (General Purpose Input/Output): code থেকে control করা pin — button পড়া, LED জ্বালানো।
Timer/Counter: clock tick গোনে; delay, সময় মাপা, আর PWM-এর (motor speed, LED dimming) কাজে লাগে।
ADC (Analog-to-Digital Converter): analog voltage-কে (temperature sensor, light sensor) সংখ্যায় বদলায়।
UART: simple serial communication, দুই তার (TX/RX) — Arduino এভাবেই PC-র সাথে কথা বলে। Related: অন্য chip-এর সাথে কথা বলতে SPI আর I2C।
Flash / EEPROM: non-volatile memory, যেখানে program আর saved settings থাকে।

কোনটা কোথায় use হয়

Microprocessor: PC, laptop, phone-এর application processor, server — যেখানে অনেক রকম বড় program চলে।
Microcontroller: embedded system — washing machine, microwave, গাড়ির engine control (ECU), TV remote, smart bulb, drone-এর flight controller, IoT sensor। একটা আধুনিক গাড়িতে কয়েক ডজন MCU থাকে।
Arduino: AVR ATmega328P microcontroller (8-bit, 16 MHz, 2 KB RAM, 32 KB flash, Harvard architecture) দিয়ে বানানো beginner-friendly board। MCU-র যে আশেপাশে প্রায় কিছুই লাগে না, এটা তার দারুণ প্রমাণ।

Example:

AVR microcontroller vs Intel 80386 microprocessor — a concrete pair the exam loves:

AVR (e.g., ATmega328P): everything on one chip — flash program memory, SRAM, EEPROM, GPIO pins, timers, ADC, UART. It is an 8-bit RISC with Harvard architecture, so most instructions run in a single cycle. It sips milliwatts — perfect for battery devices. Add power and a clock, and it just runs.
80386 (an MPU): only a 32-bit CISC CPU on the chip. It cannot do anything alone — it needs an external chipset: RAM chips, ROM/BIOS, interrupt controller, DMA controller, I/O chips, all on a motherboard. More raw computing power, but higher cost, higher watts, and a whole board of support chips.

One line to remember: the AVR is a complete computer on one chip built for cheap low-power control; the 80386 is only a CPU built for general computing and depends on external hardware for everything else.

AVR microcontroller vs Intel 80386 microprocessor — exam-এর প্রিয় একটা concrete জুটি:

AVR (যেমন ATmega328P): সব এক chip-এ — flash program memory, SRAM, EEPROM, GPIO pin, timer, ADC, UART। এটা 8-bit RISC, Harvard architecture — তাই বেশিরভাগ instruction single cycle-এ চলে। খরচ মাত্র milliwatt — battery device-এর জন্য perfect। Power আর clock দিলেই চলা শুরু।
80386 (একটা MPU): chip-এ শুধু একটা 32-bit CISC CPU। একা কিছুই করতে পারে না — লাগে external chipset: RAM chip, ROM/BIOS, interrupt controller, DMA controller, I/O chip, সব একটা motherboard-এ। Raw computing power বেশি, কিন্তু দাম বেশি, watt বেশি, আর পুরো এক board support chip লাগে।

মনে রাখার এক লাইন: AVR হলো এক chip-এ complete computer, সস্তায় কম power-এ control-এর জন্য; 80386 শুধু একটা CPU, general computing-এর জন্য, বাকি সবকিছুর জন্য external hardware-এর উপর নির্ভরশীল।

Note: Asked October 2017: "Compare an AVR microcontroller with the 80386 microprocessor." Structure the answer as: what is on the chip (AVR: CPU + flash + RAM + GPIO + timers + ADC; 386: CPU only), instruction style (single-cycle RISC vs multi-cycle CISC), power (milliwatts vs watts), and what each needs around it (almost nothing vs a full external chipset). October 2017-এ এসেছে: "AVR microcontroller-এর সাথে 80386 microprocessor-এর তুলনা করো।" উত্তর সাজান এভাবে: chip-এ কী আছে (AVR: CPU + flash + RAM + GPIO + timer + ADC; 386: শুধু CPU), instruction style (single-cycle RISC vs multi-cycle CISC), power (milliwatt vs watt), আর আশেপাশে কী লাগে (প্রায় কিছুই না vs পুরো external chipset)।

Note: One-line exam answer: a microprocessor is only a CPU and needs external memory and I/O; a microcontroller has CPU, memory, and I/O all on one chip, so it is a complete single-chip computer for embedded control. One-line exam answer: microprocessor শুধু একটা CPU, বাইরের memory আর I/O লাগে; microcontroller-এ CPU, memory, I/O সব এক chip-এ, তাই এটা embedded control-এর জন্য একটা complete single-chip computer।

Practice Questions (Admission Style)Practice Questions (Admission Style)

Q1. The key idea of the Von Neumann architecture is:

(a) Separate memories for program and data
(b) Program and data stored in the same memory
(c) No memory at all, only registers
(d) Two CPUs sharing one memory

Q1. Von Neumann architecture-এর মূল idea কোনটা?

(a) Program আর data-র জন্য আলাদা memory
(b) Program আর data একই memory-তে রাখা
(c) কোনো memory নেই, শুধু register
(d) দুইটা CPU এক memory share করে

Show Answerউত্তর দেখুন

Answer: (b) — Von Neumann = the "stored program" idea: instructions and data sit in one shared memory and travel on one shared bus. Separate memories (option a) is the Harvard architecture.

Answer: (b) — Von Neumann মানেই "stored program" idea: instruction আর data একই shared memory-তে থাকে, একই shared bus দিয়ে চলে। আলাদা memory (option a) হলো Harvard architecture।

Q2. Which register always holds the address of the next instruction to be fetched?

(a) IR
(b) MAR
(c) PC
(d) ACC

Q2. কোন register সবসময় পরের fetch হতে যাওয়া instruction-এর address রাখে?

(a) IR
(b) MAR
(c) PC
(d) ACC

Show Answerউত্তর দেখুন

Answer: (c) — The Program Counter (PC) holds the next instruction's address and is incremented during fetch. IR holds the current instruction itself, MAR holds whatever address is being accessed right now, ACC holds ALU results.

Answer: (c) — Program Counter (PC) পরের instruction-এর address রাখে আর fetch-এর সময় বাড়ে। IR রাখে চলতি instruction-টা, MAR রাখে এই মুহূর্তে access হওয়া address, ACC রাখে ALU-র result।

Q3. A processor has a 16-bit address bus. What is the maximum memory it can address?

(a) 16 KB
(b) 32 KB
(c) 64 KB
(d) 1 MB

Q3. একটা processor-এর address bus 16-bit। এটা সর্বোচ্চ কত memory address করতে পারবে?

(a) 16 KB
(b) 32 KB
(c) 64 KB
(d) 1 MB

Show Answerউত্তর দেখুন

Answer: (c) — Addressable locations = $2^{16} = 65{,}536$ = 64 K. With byte-addressable memory that is 64 KB. (Bonus: 20-bit → 1 MB, like the 8086.)

Answer: (c) — Addressable location = $2^{16} = 65{,}536$ = 64 K। Byte-addressable memory হলে সেটা 64 KB। (Bonus: 20-bit → 1 MB, 8086-এর মতো।)

Q4. What addressing mode is used in MOV A, #25?

(a) Direct
(b) Immediate
(c) Indirect
(d) Register indirect

Q4. MOV A, #25-এ কোন addressing mode use হয়েছে?

(a) Direct
(b) Immediate
(c) Indirect
(d) Register indirect

Show Answerউত্তর দেখুন

Answer: (b) — The # sign means the operand IS the number 25 itself, written inside the instruction. No memory lookup happens. That is immediate addressing.

Answer: (b) — # চিহ্নের মানে operand-টাই সংখ্যা 25, instruction-এর ভেতরেই লেখা। কোনো memory lookup হয় না। এটাই immediate addressing।

Q5. Which one is a characteristic of RISC (not CISC)?

(a) Variable-length instructions
(b) Many complex addressing modes
(c) Only LOAD and STORE instructions access memory
(d) Microprogrammed control unit

Q5. কোনটা RISC-এর বৈশিষ্ট্য (CISC-এর না)?

(a) Variable-length instruction
(b) অনেক complex addressing mode
(c) শুধু LOAD আর STORE instruction memory access করে
(d) Microprogrammed control unit

Show Answerউত্তর দেখুন

Answer: (c) — RISC is a "load-store architecture": only LOAD/STORE touch memory; everything else works register-to-register. Options (a), (b), (d) are all classic CISC traits.

Answer: (c) — RISC হলো "load-store architecture": শুধু LOAD/STORE memory touch করে; বাকি সব কাজ register-to-register। Option (a), (b), (d) সবই classic CISC বৈশিষ্ট্য।

Q6. Instruction 2 reads register R1 immediately after instruction 1 writes R1. In a pipeline, this causes a:

(a) Structural hazard
(b) Data hazard (RAW)
(c) Control hazard
(d) Page fault

Q6. Instruction 1 register R1-এ লেখার ঠিক পরেই instruction 2 R1 পড়ে। Pipeline-এ এতে হয়:

(a) Structural hazard
(b) Data hazard (RAW)
(c) Control hazard
(d) Page fault

Show Answerউত্তর দেখুন

Answer: (b) — Reading a value before the earlier instruction has written it back is a Read-After-Write (RAW) data hazard. It is fixed by forwarding, or by stalling if forwarding is not enough.

Answer: (b) — আগের instruction result write back করার আগেই value পড়া মানে Read-After-Write (RAW) data hazard। Forwarding দিয়ে fix হয়, আর forwarding যথেষ্ট না হলে stall দিয়ে।

Q7. A loop executes the same 10 instructions one million times. The cache keeps serving them fast. This mainly shows:

(a) Spatial locality
(b) Temporal locality
(c) Write-back policy
(d) DMA transfer

Q7. একটা loop একই 10টা instruction দশ লাখ বার চালায়। Cache সেগুলো fast serve করতে থাকে। এটা মূলত কী দেখায়?

(a) Spatial locality
(b) Temporal locality
(c) Write-back policy
(d) DMA transfer

Show Answerউত্তর দেখুন

Answer: (b) — The same addresses are reused again and again over time → temporal locality. Spatial locality would be about touching neighboring addresses, like walking through an array.

Answer: (b) — একই address সময়ের সাথে বারবার use হচ্ছে → temporal locality। Spatial locality হতো পাশের address touch করা নিয়ে, যেমন array ধরে ধরে হাঁটা।

Q8. The main benefit of DMA is:

(a) The CPU moves data faster byte by byte
(b) Devices become faster than the CPU
(c) Data moves between device and memory without the CPU copying every byte
(d) Interrupts are completely removed from the system

Q8. DMA-র প্রধান সুবিধা কী?

(a) CPU byte byte করে আরো দ্রুত data সরায়
(b) Device CPU-এর চেয়ে fast হয়ে যায়
(c) CPU-কে প্রতিটা byte copy করতে না দিয়েই data device আর memory-র মধ্যে যায়
(d) System থেকে interrupt পুরোপুরি উঠে যায়

Show Answerউত্তর দেখুন

Answer: (c) — The DMA controller does the copying itself; the CPU is free to do other work and receives just one interrupt when the whole block is done. Interrupts are not removed (d) — they are reduced to one per block.

Answer: (c) — DMA controller নিজেই copy করে; CPU অন্য কাজে free থাকে আর পুরো block শেষ হলে মাত্র একটা interrupt পায়। Interrupt উঠে যায় না (d) — প্রতি block-এ একটায় নেমে আসে।

Q9. (Written) Memory holds M[300] = 400, M[400] = 700, M[700] = 900, and register R2 = 400. For each instruction below, name the addressing mode and the final value loaded into ACC:

LOAD #300
LOAD 300
LOAD (300)
LOAD (R2)

Q9. (Written) Memory-তে আছে M[300] = 400, M[400] = 700, M[700] = 900, আর register R2 = 400। নিচের প্রতিটা instruction-এর addressing mode আর ACC-তে আসা final value লিখুন:

LOAD #300
LOAD 300
LOAD (300)
LOAD (R2)

Show Answerউত্তর দেখুন

Answer:

Immediate — ACC = 300 (the number itself, no memory access).
Direct — ACC = M[300] = 400 (one memory access).
Indirect — first read M[300] = 400 (this is the address), then ACC = M[400] = 700 (two memory accesses).
Register indirect — R2 holds the address 400, so ACC = M[400] = 700 (one memory access; the address came from a register).

Answer:

Immediate — ACC = 300 (সংখ্যাটাই, কোনো memory access নেই)।
Direct — ACC = M[300] = 400 (একটা memory access)।
Indirect — আগে M[300] = 400 পড়া হয় (এটা address), তারপর ACC = M[400] = 700 (দুইটা memory access)।
Register indirect — R2-তে address 400 আছে, তাই ACC = M[400] = 700 (একটা memory access; address এসেছে register থেকে)।

Q10. (Written) Write programs to evaluate $ X = (A - B) + (C \times D) $ using (i) a 3-address machine, (ii) a 1-address (accumulator) machine, and (iii) a 0-address (stack) machine.

Q10. (Written) $ X = (A - B) + (C \times D) $ evaluate করার program লিখুন (i) 3-address machine, (ii) 1-address (accumulator) machine, আর (iii) 0-address (stack) machine দিয়ে।

Show Answerউত্তর দেখুন

Answer:

(i) 3-address:

SUB R1, A, B      ; R1 = A - B
MUL R2, C, D      ; R2 = C * D
ADD X,  R1, R2    ; X = R1 + R2

(ii) 1-address (do the multiply first, save it, then add):

LOAD  C           ; ACC = C
MUL   D           ; ACC = C * D
STORE T           ; T = C * D
LOAD  A           ; ACC = A
SUB   B           ; ACC = A - B
ADD   T           ; ACC = (A-B) + (C*D)
STORE X

(iii) 0-address. Postfix of the expression: A B - C D * +:

PUSH A
PUSH B
SUB               ; top = A - B
PUSH C
PUSH D
MUL               ; top = C * D
ADD               ; top = (A-B)+(C*D)
POP  X

Answer:

(i) 3-address:

SUB R1, A, B      ; R1 = A - B
MUL R2, C, D      ; R2 = C * D
ADD X,  R1, R2    ; X = R1 + R2

(ii) 1-address (আগে multiply করে save, তারপর add):

LOAD  C           ; ACC = C
MUL   D           ; ACC = C * D
STORE T           ; T = C * D
LOAD  A           ; ACC = A
SUB   B           ; ACC = A - B
ADD   T           ; ACC = (A-B) + (C*D)
STORE X

(iii) 0-address। Expression-এর postfix: A B - C D * +:

PUSH A
PUSH B
SUB               ; top = A - B
PUSH C
PUSH D
MUL               ; top = C * D
ADD               ; top = (A-B)+(C*D)
POP  X

Q11. (Written) A 4-stage pipeline has a clock cycle of 10 ns and runs 200 instructions. Find (i) non-pipelined time, (ii) pipelined time, (iii) speedup, and (iv) the maximum possible speedup.

Q11. (Written) একটা 4-stage pipeline-এর clock cycle 10 ns, 200টা instruction চালায়। বের করুন (i) pipeline ছাড়া সময়, (ii) pipeline সহ সময়, (iii) speedup, আর (iv) সর্বোচ্চ সম্ভব speedup।

Show Answerউত্তর দেখুন

Answer: Here $k = 4$, $n = 200$, $t = 10$ ns.

Non-pipelined: $n \cdot k \cdot t = 200 \times 4 \times 10 = 8000$ ns.
Pipelined: $(k + n - 1)\,t = (4 + 200 - 1) \times 10 = 203 \times 10 = 2030$ ns.
Speedup: $8000 / 2030 \approx 3.94$.
Maximum speedup = number of stages = $k = 4$ (reached only as $n \to \infty$).

Answer: এখানে $k = 4$, $n = 200$, $t = 10$ ns।

Pipeline ছাড়া: $n \cdot k \cdot t = 200 \times 4 \times 10 = 8000$ ns।
Pipeline সহ: $(k + n - 1)\,t = (4 + 200 - 1) \times 10 = 203 \times 10 = 2030$ ns।
Speedup: $8000 / 2030 \approx 3.94$।
সর্বোচ্চ speedup = stage সংখ্যা = $k = 4$ (শুধু $n \to \infty$ হলে পৌঁছায়)।

Q12. (Written) A direct-mapped cache is 16 KB with 32-byte blocks. The machine uses 32-bit addresses. (i) How many lines does the cache have? (ii) Find the number of offset, index, and tag bits. (iii) Which line does memory block number 1030 map to?

Q12. (Written) একটা direct-mapped cache 16 KB, block 32 byte। Machine-টা 32-bit address use করে। (i) Cache-এ কয়টা line? (ii) Offset, index, tag bit কয়টা করে? (iii) Memory block number 1030 কোন line-এ map হবে?

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Answer:

Lines = cache size ÷ block size = $16\,\text{KB} / 32\,\text{B} = 2^{14}/2^5 = 2^9 = \mathbf{512}$ lines.
Offset = $\log_2 32 = \mathbf{5}$ bits. Index = $\log_2 512 = \mathbf{9}$ bits. Tag = $32 - 9 - 5 = \mathbf{18}$ bits. Address = [18 | 9 | 5].
Line = block number mod lines = $1030 \bmod 512 = 1030 - 1024 = \mathbf{6}$. So block 1030 goes to line 6.

Answer:

Line = cache size ÷ block size = $16\,\text{KB} / 32\,\text{B} = 2^{14}/2^5 = 2^9 = \mathbf{512}$ টা line।
Offset = $\log_2 32 = \mathbf{5}$ bit। Index = $\log_2 512 = \mathbf{9}$ bit। Tag = $32 - 9 - 5 = \mathbf{18}$ bit। Address = [18 | 9 | 5]।
Line = block number mod line সংখ্যা = $1030 \bmod 512 = 1030 - 1024 = \mathbf{6}$। তাই block 1030 যাবে line 6-এ।

Q13. (Written) A system has: L1 hit time = 1 ns, L1 miss rate = 10%; L2 access time = 10 ns, L2 miss rate = 20%; main memory access = 100 ns. (i) Find the AMAT. (ii) What would the AMAT be with no L2 at all?

Q13. (Written) একটা system-এ: L1 hit time = 1 ns, L1 miss rate = 10%; L2 access time = 10 ns, L2 miss rate = 20%; main memory access = 100 ns। (i) AMAT বের করুন। (ii) L2 একদম না থাকলে AMAT কত হতো?

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Answer:

With L2: L2 miss penalty for L1 = $10 + 0.20 \times 100 = 30$ ns. So AMAT = $1 + 0.10 \times 30 = \mathbf{4\ ns}$.
Without L2: every L1 miss goes straight to memory. AMAT = $1 + 0.10 \times 100 = \mathbf{11\ ns}$.

The L2 cache cuts the average from 11 ns to 4 ns — this is why multi-level caches exist.

Answer:

L2 সহ: L1-এর জন্য miss penalty = $10 + 0.20 \times 100 = 30$ ns। তাহলে AMAT = $1 + 0.10 \times 30 = \mathbf{4\ ns}$।
L2 ছাড়া: প্রতিটা L1 miss সরাসরি memory-তে যায়। AMAT = $1 + 0.10 \times 100 = \mathbf{11\ ns}$।

L2 cache গড় সময় 11 ns থেকে 4 ns-এ নামিয়ে আনে — এজন্যই multi-level cache আছে।

Q14. (Written) In an 8086 system, CS = 2500H and IP = 1400H. (i) Compute the physical address of the next instruction. (ii) Why does the 8086 need this segment:offset trick at all?

Q14. (Written) একটা 8086 system-এ CS = 2500H আর IP = 1400H। (i) পরের instruction-এর physical address বের করুন। (ii) 8086-এর এই segment:offset trick আদৌ লাগে কেন?

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Answer:

Physical address = Segment × 16 + Offset = $2500\text{H} \times 10\text{H} + 1400\text{H} = 25000\text{H} + 1400\text{H} = \mathbf{26400H}$.
The 8086's registers are only 16-bit (max 64 KB), but its address bus is 20-bit (1 MB). Combining two 16-bit values as segment×16 + offset produces a 20-bit address, letting 16-bit registers reach the full 1 MB.

Answer:

Physical address = Segment × 16 + Offset = $2500\text{H} \times 10\text{H} + 1400\text{H} = 25000\text{H} + 1400\text{H} = \mathbf{26400H}$।
8086-এর register মাত্র 16-bit (সর্বোচ্চ 64 KB), কিন্তু address bus 20-bit (1 MB)। দুইটা 16-bit value-কে segment×16 + offset হিসেবে মেলালে 20-bit address পাওয়া যায়, ফলে 16-bit register দিয়েই পুরো 1 MB reach করা যায়।

Q15. (Written, hard) A 5-stage pipeline (IF, ID, EX, MEM, WB) runs 6 instructions. Instruction I3 depends on a LOAD result of I2, and the hardware must insert 2 stall cycles before I3's EX stage. (i) How many cycles do the 6 instructions take with no hazards? (ii) How many cycles with the 2 stalls? (iii) What single hardware technique could reduce (but here not fully remove) such stalls?

Q15. (Written, hard) একটা 5-stage pipeline (IF, ID, EX, MEM, WB) 6টা instruction চালায়। Instruction I3, I2-এর একটা LOAD result-এর উপর depend করে, আর hardware-কে I3-এর EX stage-এর আগে 2টা stall cycle ঢোকাতে হয়। (i) কোনো hazard না থাকলে 6টা instruction-এ কত cycle লাগত? (ii) 2টা stall সহ কত cycle লাগবে? (iii) কোন একটা hardware technique এমন stall কমাতে (কিন্তু এখানে পুরোপুরি সরাতে না) পারত?

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Answer:

No hazards: cycles = $k + n - 1 = 5 + 6 - 1 = \mathbf{10}$ cycles.
Each stall adds exactly 1 cycle to the total, because I3 and everything behind it slide right by one cycle per stall. Total = $10 + 2 = \mathbf{12}$ cycles.
Forwarding (bypassing) — sending results straight from EX/MEM outputs to the next instruction's EX input. For a LOAD-use dependency the data only exists after MEM, so even with forwarding one stall usually remains (the classic "load-use delay"); here it would cut 2 stalls down to 1, not 0.

Answer:

Hazard ছাড়া: cycle = $k + n - 1 = 5 + 6 - 1 = \mathbf{10}$ cycle।
প্রতিটা stall মোটে ঠিক 1 cycle যোগ করে, কারণ I3 আর তার পেছনের সবকিছু প্রতি stall-এ এক cycle করে ডানে সরে যায়। মোট = $10 + 2 = \mathbf{12}$ cycle।
Forwarding (bypassing) — result-কে EX/MEM output থেকে সরাসরি পরের instruction-এর EX input-এ পাঠানো। LOAD-use dependency-তে data আসে MEM-এর পরে, তাই forwarding থাকলেও সাধারণত একটা stall থেকেই যায় (classic "load-use delay"); এখানে 2টা stall কমে 1টা হতো, 0 হতো না।

Q16. (Written, real exam style — April 2019) Your CPU has no PUSH or POP instruction. Using only mov and add-type (add/sub) instructions, write the code for (i) PUSH R1 and (ii) POP R1. Assume the stack grows downward and SP points to the current top item. (iii) Why must PUSH change SP before writing, while POP must read before changing SP?

Q16. (Written, real exam style — April 2019) আপনার CPU-তে PUSH বা POP instruction নেই। শুধু mov আর add-type (add/sub) instruction দিয়ে (i) PUSH R1 আর (ii) POP R1-এর code লিখুন। ধরে নিন stack নিচের দিকে বাড়ে আর SP বর্তমান top item-টা point করে। (iii) PUSH কেন লেখার আগে SP বদলায়, আর POP কেন SP বদলানোর আগে পড়ে?

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Answer:

(i) PUSH R1 (stack grows down, so make room first):

sub sp, sp, #1     ; make room: SP moves DOWN (or: add sp, sp, -1)
mov [sp], R1       ; store R1 at the new top

(ii) POP R1 (read first, then shrink):

mov R1, [sp]       ; copy the top item into R1
add sp, sp, #1     ; SP moves UP: the old slot is free

(iii) SP always points at valid data (the top). PUSH must first create an empty slot and then fill it — writing first would overwrite the current top. POP must read the top while SP still points at it — moving SP first would make it read a free/garbage slot. Note that PUSH makes SP smaller because the stack grows toward lower addresses.

Answer:

(i) PUSH R1 (stack নিচে বাড়ে, তাই আগে জায়গা):

sub sp, sp, #1     ; জায়গা বানাও: SP নিচে নামে (বা: add sp, sp, -1)
mov [sp], R1       ; নতুন top-এ R1 store করো

(ii) POP R1 (আগে পড়ো, তারপর ছোট করো):

mov R1, [sp]       ; top-এর item R1-এ copy করো
add sp, sp, #1     ; SP উপরে ওঠে: পুরানো slot free

(iii) SP সবসময় valid data (top) point করে। PUSH-কে আগে খালি slot বানিয়ে তারপর ভরতে হয় — আগে লিখলে বর্তমান top overwrite হয়ে যেত। POP-কে top পড়তে হয় যখন SP এখনো সেটাই point করছে — আগে SP সরালে free/garbage slot পড়া হতো। খেয়াল করুন PUSH-এ SP ছোট হয়, কারণ stack ছোট address-এর দিকে বাড়ে।

Q17. (Written, real exam style) (i) What is a superscalar microprocessor? How is it different from a simple pipelined (scalar) processor? (ii) A memory system uses 4 interleaved banks; each bank's access time is 80 ns. For long sequential reads, what is the best-case effective time per word, and why?

Q17. (Written, real exam style) (i) Superscalar microprocessor কী? Simple pipelined (scalar) processor থেকে এটা কীভাবে আলাদা? (ii) একটা memory system 4টা interleaved bank use করে; প্রতিটা bank-এর access time 80 ns। লম্বা sequential read-এর জন্য best-case effective time per word কত, আর কেন?

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Answer:

A superscalar microprocessor issues more than one instruction per clock cycle, using duplicate functional units (multiple ALUs, separate load/store units) and hardware that picks independent instructions to run together. A scalar pipelined processor only overlaps the stages of instructions — at most 1 instruction finishes per cycle (best CPI = 1). A superscalar can finish 2 or more per cycle (CPI < 1), like several pipelines side by side.
Consecutive words go to different banks (address $i$ → bank $i \bmod 4$), so up to 4 accesses overlap in time. Best case the memory delivers 4 words per 80 ns → effective time per word = $80 / 4 = \mathbf{20}$ ns, a 4× bandwidth gain over a single bank (which gives one word per 80 ns).

Answer:

Superscalar microprocessor প্রতি clock cycle-এ একাধিক instruction issue করে, duplicate functional unit (একাধিক ALU, আলাদা load/store unit) আর independent instruction বেছে একসাথে চালানোর hardware দিয়ে। Scalar pipelined processor শুধু instruction-এর stage overlap করে — প্রতি cycle-এ সর্বোচ্চ 1টা instruction শেষ হয় (best CPI = 1)। Superscalar প্রতি cycle-এ 2 বা তার বেশি শেষ করতে পারে (CPI < 1), যেন কয়েকটা pipeline পাশাপাশি।
পরপর word আলাদা bank-এ যায় (address $i$ → bank $i \bmod 4$), তাই সর্বোচ্চ 4টা access সময়ে overlap করে। Best case-এ memory প্রতি 80 ns-এ 4টা word দেয় → effective time per word = $80 / 4 = \mathbf{20}$ ns, এক bank-এর তুলনায় (যেটা প্রতি 80 ns-এ 1 word দেয়) 4× bandwidth লাভ।

Q18. (Written, real exam style — October 2017) (i) Explain, step by step, how a computer performs division using the shift-and-subtract (restoring division) method. (ii) Trace the division of 11 by 3 in 4-bit binary, showing A and Q after every step, and state the quotient and remainder.

Q18. (Written, real exam style — October 2017) (i) Shift-and-subtract (restoring division) method-এ computer কীভাবে division করে, step by step ব্যাখ্যা করুন। (ii) 4-bit binary-তে 11 কে 3 দিয়ে ভাগের trace দেখান — প্রতিটা step-এর পরে A আর Q লিখুন, আর quotient ও remainder বলুন।

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Answer:

(i) Put the dividend in Q, the divisor in M, and set A = 0. Repeat once per bit: shift (A, Q) left one bit; try A = A − M; if there is no borrow (A ≥ 0), set Q₀ = 1; if there is a borrow, restore A by adding M back and set Q₀ = 0. After n steps, Q is the quotient and A is the remainder.

(ii) Q = 1011 (11), M = 0011 (3), A = 0000:

Step	After shift (A, Q)	Try A − M	Borrow?	Action	A	Q
Init	—	—	—	—	0000	1011
1	A = 0001, Q = 011_	0001 − 0011 < 0	Yes	Restore, Q₀ = 0	0001	0110
2	A = 0010, Q = 110_	0010 − 0011 < 0	Yes	Restore, Q₀ = 0	0010	1100
3	A = 0101, Q = 100_	0101 − 0011 = 0010	No	Keep, Q₀ = 1	0010	1001
4	A = 0101, Q = 001_	0101 − 0011 = 0010	No	Keep, Q₀ = 1	0010	0011

Q = 0011 = 3 (quotient), A = 0010 = 2 (remainder). Check: $11 = 3 \times 3 + 2$. Correct.

Answer:

(i) Dividend রাখুন Q-তে, divisor রাখুন M-এ, A = 0 করুন। প্রতি bit-এর জন্য repeat: (A, Q) এক bit বামে shift; A = A − M চেষ্টা; borrow না হলে (A ≥ 0) Q₀ = 1; borrow হলে M যোগ করে A restore আর Q₀ = 0। n step-এর পরে Q হলো quotient আর A হলো remainder।

(ii) Q = 1011 (11), M = 0011 (3), A = 0000:

Step	Shift-এর পরে (A, Q)	A − M চেষ্টা	Borrow?	Action	A	Q
Init	—	—	—	—	0000	1011
1	A = 0001, Q = 011_	0001 − 0011 < 0	হ্যাঁ	Restore, Q₀ = 0	0001	0110
2	A = 0010, Q = 110_	0010 − 0011 < 0	হ্যাঁ	Restore, Q₀ = 0	0010	1100
3	A = 0101, Q = 100_	0101 − 0011 = 0010	না	রাখো, Q₀ = 1	0010	1001
4	A = 0101, Q = 001_	0101 − 0011 = 0010	না	রাখো, Q₀ = 1	0010	0011

Q = 0011 = 3 (quotient), A = 0010 = 2 (remainder)। Check: $11 = 3 \times 3 + 2$। ঠিক আছে।

Q19. (Written, real exam style — October 2017 & October 2018) (i) The Pentium is called a superscalar processor, but the 80386 is not. Explain why. (ii) Give any four differences between CISC and RISC (the October 2018 paper asked this as a flow diagram — a table or two labeled flows both earn marks).

Q19. (Written, real exam style — October 2017 & October 2018) (i) Pentium-কে superscalar processor বলা হয়, কিন্তু 80386-কে না। কেন, ব্যাখ্যা করুন। (ii) CISC আর RISC-এর যেকোনো চারটা পার্থক্য লিখুন (October 2018-এর paper-এ এটা flow diagram আকারে চেয়েছিল — table বা দুইটা labeled flow, দুটোতেই marks পাবেন)।

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Answer:

The Pentium has two integer pipelines — the U pipe and the V pipe. When two neighboring instructions are simple and independent, it issues one to each pipe in the same clock cycle, completing up to 2 instructions per cycle (CPI < 1). Issuing more than one instruction per cycle is the definition of superscalar. The 80386 has only one pipeline, so it can never issue more than 1 instruction per cycle — it is a scalar processor.
Any four of: (1) RISC has few simple instructions, CISC has many complex ones; (2) RISC instructions are fixed length, CISC variable length; (3) RISC runs most instructions in 1 cycle, CISC takes multiple cycles; (4) in RISC only LOAD/STORE touch memory, in CISC many instructions can; (5) RISC uses hardwired control, CISC uses microprogrammed control; (6) RISC pipelines easily, CISC is harder to pipeline. As a flow diagram: CISC — complex instruction → microprogrammed control splits it into micro-steps → multiple cycles → result; RISC — simple fixed-size instruction → hardwired decode → 1 cycle in pipeline → result.

Answer:

Pentium-এ দুইটা integer pipeline আছে — U pipe আর V pipe। পাশাপাশি দুইটা instruction simple আর independent হলে এটা একই clock cycle-এ দুই pipe-এ একটা করে issue করে — প্রতি cycle-এ 2টা পর্যন্ত instruction শেষ হয় (CPI < 1)। প্রতি cycle-এ একাধিক instruction issue করাই superscalar-এর definition। 80386-এ pipeline মাত্র একটা, তাই প্রতি cycle-এ 1টার বেশি issue কখনোই পারে না — এটা scalar processor।
যেকোনো চারটা: (1) RISC-এ অল্প simple instruction, CISC-এ অনেক complex; (2) RISC instruction fixed length, CISC variable length; (3) RISC-এ বেশিরভাগ instruction 1 cycle-এ, CISC-এ একাধিক cycle; (4) RISC-এ শুধু LOAD/STORE memory touch করে, CISC-এ অনেক instruction-ই পারে; (5) RISC-এ hardwired control, CISC-এ microprogrammed control; (6) RISC-এ pipelining সহজ, CISC-এ কঠিন। Flow diagram আকারে: CISC — complex instruction → microprogrammed control micro-step-এ ভাঙে → একাধিক cycle → result; RISC — simple fixed-size instruction → hardwired decode → pipeline-এ 1 cycle → result।